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                                                       Industry Sponsored Projects

Sponsored Projects:


Microwave FET Modeling
Project Assistant :   Scarlet Halabi
Project Director  :   Dr. Prasad Shastry
2002
This project was supported by a research grant from Fujitsu Compound Semiconductor, Inc.

ABSTRACT
   In this project, microwave transistor modeling is presented. This project involves the measurement procedures (i.e. measured DC and RF characteristics of the device), the parameter extraction of the model using the measured values, the design of model validation by comparing the measured data with the modeled data, as well as parameter optimization needed. Finally, a flow chart shows a summary of the modeling technique presented in this project.

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Active Bias, Power Detector and Voltage Controlled Attenuator MMICs
Project Assistant :   Scarlet Halabi
Project Director  :   Dr. Prasad Shastry
Summer 2002
This project was supported by a research grant from Fujitsu Compound Semiconductor, Inc.

ABSTRACT
   This graduate thesis project involves the design of three monolithic microwave integrated circuits in the 24 - 42 GHz frequency range: active bias circuit, power detector circuit, and voltage controlled attenuator circuit. The first two circuits have been fabricated using Gallium Arsenide technology and tested, while the third circuit still awaits fabrication and testing.

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Tests and Measurements of GPS Receivers
Project Assistant :   Scarlet Halabi
Project Director  :   Dr. Prasad Shastry
December 2001
This project was supported by a research grant from Tracking and Imaging Systems, Inc.

ABSTRACT
   Coming soon...

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MMIC Band-Pass Cascode Cell Distributed Amplifiers
Project Assistant :   Shawn Parker
Project Director  :   Dr. Prasad Shastry
June 2001
This project was supported by a research grant from Fujitsu Compound Semiconductor, Inc.

ABSTRACT
   The design and analysis of 24 to 42 GHz MMIC Band-Pass Cascode Cell Distributed Amplifiers as presented in this thesis. The amplifiers make use of a novel mixed topology consisting of a band-pass gate line and a low-pass drain line. The mixed topology provides the benefits of a band-pass topology without requiring additional elements in the drain line. The amplifier makes use of a pHEMT cascode gain cell capacitively coupled to the gate line. Two amplifiers, utilizing 200 micrometer and 300 micrometer pHEMTs, have been designed, fabricated and tested. The amplifiers are suited for application in European Local Multipoint Distribution Systems for driving power amplifiers.

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Transimpedance Amplifiers for Optoelectronic Applications
Project Assistant :   Shawn Parker
Project Director  :   Dr. Prasad Shastry
December 2000
This project was supported by a research grant from Fujitsu Compound Semiconductor, Inc.

ABSTRACT
   The optoelectronic field deals with the transition between optical and electrical components. Transimpedance amplifiers are used in optoelectronic applications. The optoelectronic conversion deals with two fundamental specifications that are used to define the term "Transimpedance Amplifiers". The optical devices generally have input impedances that vary significantly from the impedance levels encountered in RF/microwave circuits.
   The term transimpedance amplifier can be defined as an amplifier that provides gain and an impedance transformation. Bandwidth is a high priority in transimpedance amplifiers. These amplifiers have to maintain an acceptable response down to very low frequencies and still perform satisfactorily at high frequencies.
   Conventional amplifiers have been designed for transimpedance applications to provide the necessary bandwidth for high data rates. Optical devices typically have low input impedances.
   The distributed amplifier can meet the challenge of matching, and providing gain between these two very different impedance levels over an extremely wide bandwidth. The ability of the distributed structure in a distributed amplifier to provide extremely wideband matching is dependent on the gain cell.
   The constraints in the design of distributed transimpedance amplifier are the device characteristics and the biasing networks. Biasing networks are an extremely important part of the design. The biasing network could limit the low frequency response of the amplifier.

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Wide-Band Impedance Transformation Techniques
Project Assistant :   Shawn Parker
Project Director  :   Dr. Prasad Shastry
December 2000
This project was supported by a research grant from Fujitsu Compound Semiconductor, Inc.

ABSTRACT
   Impedance matching problems are encountered involved in most RF circuit designs. Impedance matching techniques can be divided into two categories: Narrow-band matching techniques and Wide-band matching techniques.
   This study focuses on wide-band matching techniques. The wide-band impedance matching techniques are significantly more compled than the narrow-band techniques. To fully understand wide-band impedance matching requires years of dedicated study. However, a designer can, in a shorter period, understand the principles of wide-band impedance matching. To understanding of the principles is adequate to intelligently utilize the impedance matching software packages.
   A summary of wide-band impedance matching techniques is provided in this report. The limits of the Bode-Fano criteria are presented to provide an understanding of the performance limits of a matching network. Two wide-band impedance matching techniques are presented. Both, the Real Frequency Technique (RFT), and the Q-Transform Technique (QTT) are used to design wide-band impedance matching networks. Examples of networks designed using each technique are presented and evaluated. The realizability of the networks is also discussed.

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Introduction to MMIC Design; MMIC Technology: Processing, Modeling and Component Design
Project Assistant :   Scarlet Halabi
Project Director  :   Dr. Prasad Shastry
December 2000
This project was supported by a research grant from Fujitsu Compound Semiconductor, Inc.

ABSTRACT
   The processes of fabricating GaAs MMICs are described in Chapter 1. Several options are described for each step in the process along with their advantages and disadvantages. The design of the MMIC is shown to be limited by the process technology that is available. The understanding of each process step leads to appropriate design considerations for the designer of GaAs MMICs.
   The fundamental information for MESFETs, HEMTs, and HBTs is reviewed in Chapter 2. The principles of operation of each device are described. The advantages and disadvantages as well as applications and limitations for each device are discussed. A comparative study of the different device models is included, and a study of the figures of merit is reported.
   The designs and simulations of a coupled line directional coupler and a square spiral inductor are presented in Chapter 3.

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Tests and Measurements of GPS Receivers
Project Assistant :   Sasidhar Vajha
Project Director  :   Dr. Prasad Shastry
April 2000
This project was supported by a research grant from Tracking and Imaging Systems, Inc.

ABSTRACT
   Coming soon...

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A PCB Element Model for 8-pin SOIC Plastic Package
Project Assistant :   Sunil Modur
Project Director  :   Dr. Prasad Shastry
April 2000
This project was supported by a research grant from Northrop Grumman Corp.

ABSTRACT
   A 8-pin SOIC package model has been developed using printed circuit board ( PCB ) elements present in the HPEEsof library. The model has been simulated on HPEEsof ( Series IV, Version 6.1 ), the high frequency simulation software. The de-embedded S-parameters of the chip ( AGBW953 GaAs MMIC amplifier ) in the SOIC package, obtained through measurements and simulations are compared.

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A Software for de-embedding 2-port S-parameters
Project Assistant :   Sunil Modur
Project Director  :   Dr. Prasad Shastry
April 2000
This project was supported by a research grant from Northrop Grumman Corp.

ABSTRACT
    Software for de-embedding two-port S-parameters using TRL technique procedure, coded in Matlab, has been developed. The code has been verified by de-embedding NE76084S packaged transistor S-parameters. The software contains the following: 1. modi.m - TRL de-embedding software written in Matlab ( Need Matlab Software to run the code). 2. dut.s2p - S-parameter file to which the de-embedded S-parameter are to be compared ( NE76084S Packaged transistor S-parameters ). 3. dut1.s2p - S-parameter file of the DUT ( NE76084S Packaged transistor ) measured with "Il" and "Ir". 4. line.s2p - S-parameters of the line standard. 5. thru.s2p - S-parameters of the thru standard. 6. open.s1p - S-parameters of the open standard. 7. deemtransis.xls - De-embedded S-parameters ( Microsoft Excel file ).

Publications : 1) J. P. Hondal, " Propagation Constant Determination in Microwave Fixture De-embedding Procedure ",
                               IEEE Transition Microwave Theory and Technique, 
                              Vol. 36, No. 4, April 1998, pp. 706-714.


 

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A Lumped Element Model for 8-pin SOIC Plastic Package
Project Assistant :   Thirendra Rayamajhi
Project Director  :   Dr. Prasad Shastry
September 1999
This project was supported by a research grant from Northrop Grumman Corp.

ABSTRACT
    A lumped element model for an 8-pin SOIC package using transmission line elements is developed. All the package parasitics are calculated from the physical dimensions and the electrical properties of the package materials and the test board. The model is simulated on the linear bench of HPEEsof CAD tools ( Series IV, Version 6.1), where equations and variables have been used to calculate the model parameters. Hence, input to the model are in the form of physical dimensions of leads and bond wires, and relative permittivities and loss tangents of the package materials and the test board. The model is optimized such that the simulated S-parameter magnitudes are within 10 % of the measured results. 

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A Lumped Element Model for LTCC Buried Spiral Inductor
Project Assistant :   Ed Cullerton
Project Director  :   Dr. Prasad Shastry
December 1998
This project was supported by a research grant from Northrop Grumman Corp.

ABSTRACT
    A lumped element model for a LTCC ( Low Temperature Co-Fired Ceramic ) multi-layer spiral inductor has been developed. The model is developed using analytical equations to calculate the electrical parameters of the inductor. The lumped element model is simulated, and the simulated results are compared to measured results. The model shows good agreement with measured S-parameters from 0.5 to 4 GHz. Guidelines for the development of the lumped element model are given.

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SOIC and LTCC Package Modeling
This project was supported by a grant from Electronics and Systems Integration Division, Northrop Grumman Corporation.
Bradley University Project Team:
Project Director      :  Dr. Prasad Shastry
Project Assistants   :  Thirendra Rayamajhi
                                     Ed Cullerton
                                     Sunil Modur
February 1998

Chapter 1 : Lumped Element Modeling of SOIC Package
by
Thirendra Rayamajhi

ABSTRACT
    This report contains the efforts that went into model an 8-pin SOIC package using transmission line elements. All the package parasitics are calculated from the physical dimensions and electrical properties of the package materials and the test board whenever applicable. The model is simulated by HPEEsof CAD tools, where equations and variables have been used to calculate the model parameters. Hence, input to the program are in the form of physical dimensions of leads and bond wires, and relative premittivities and loss tangents of the package materials and test board. The nodal responses without manual tuning or optimizing and preliminary measured S-parameters without de-embedding are compared.

Chapter 2 : Modelling of a LTCC Multi Layer Spiral Inductor
by
Ed Cullerton

ABSTRACT
    Two models of a multi-layer LTCC (Low Temperature Co-fired Ceramic) inductor have been developed. The models are based on: a) Printed Circuit Board Elements available in the HP-EEsof linear simulator, and b) Lumped element equivalent circuit developed analytically. A design procedure and a complete description of each model developed are included in this report.

Chapter 3: Computer Aided Modeling of 8-Pin SOIC Package
by
Sunil Modur

ABSTRACT
    An 8-pin SOIC package model has been developed using printed circuit board (PCB) elements present in the HPEEsof library. The model has been simulated on HPEEsof, the high frequency simulation software. the S-parameters of the chip (AGBW953 GaAs MMIC amplifier) in the package, obtained through measurements and simulations are compared.
    The procedures for de-embedding the measured S-parameters of the package in a test-fixture are presented. The de-embedding software, developed as a part of this project is included. The design of the test-fixture as well as the TRL calibration standards used in S-parameter de-embedding are detailed.

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24 GHz Proximity Sensor
Project Assistants :   Bruce E. Unger
                                   Chad Campen
Project Director  :   Dr. Prasad Shastry
May 1997
This project was supported by a research grant from Northrop Grumman Corp.

ABSTRACT
    In today's society, the need for new products to increase the safety of the individuals is apparent. Several products are now being developed in the wireless communications industry for this purpose. The 24GHz Proximity Sensor utilizes radar technology to determine and display the range of a stationary object with respect to the radar. This project can affect the world directly, especially in the automotive industry. As a result of mounting the system on the rear bumper of an automobile, the range of stationary objects behind the vehicle will be provided to the driver of the car.
    This project is designed around the Northrop Grumman TR1G946 Monolithic Microwave Integrated Circuit (MMIC) transceiver chip. Objectives include background research of the radar technology, characterization of the transceiver chip, and the system design principle to extract the range information. Utilizing multiple frequency continuous wave radar, the intermediate frequency output of the transceiver chip is a square wave if the transmitter signal is switched between two frequencies. The peak to peak amplitude of the square wave is proportional to the desired range, which can then be displayed to the driver of the automobile.

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A 2.5 GHz Programmable Frequency Divider
Project Assistant :   Srinivas Reddy Ponnala
Project Director  :   Dr. Prasad Shastry
May 1995
This project was supported by a research grant from Northrop Grumman Corp.

ABSTRACT
    A 2.5 GHz Programmable frequency divider has been designed and simulated, for use in microwave frequency synthesis applications. The frequency divider uses a 1µm gate length E/D MESFETs, and Schottky diodes. The basic building block of the frequency divider is Direct - Coupled FET Logic (DCFL) gate. Graphical design approach is used for the design of frequency divider logic circuits. Using this approach test circuits have been designed, laidout and simulated. Transmission line interconnect designs are implemented in layout and its effects are simulated. A new analytical design approach for the design of DCFL inverter is presented. The frequency divider is capable of dividing an input frequency from DC to 2.5 GHz with any divisor between 2 to 127. The delays obtained from the test circuit simulations are used  in the simulation of a 7-bit programmable frequency divider.

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A 972-998 MHz PLL Frequency Synthesizer
Project Assistants :   Gary Brubaker
                                   Shijay Dalal
                                   Zhi M. Li
Project Director    :   Dr. Prasad Shastry
June 1995
This project was supported by a research grant from Northrop Grumman Corp.

ABSTRACT
    A prototype PLL synthesizer was developed for application in a 902MHz to 928MHz wireless data transceiver. The design uses a Motorola MC 145191F PLL frequency synthesizer, mounted on a 1.5" square board. Due to the limitations of the measurement devices available, not all measurements could be performed. Phase noise specifications very close (less than 10KHz away) to the carrier could not be measured. The synthesizer locks to frequencies between 972.015MHz and 997.965MHz with 30KHz spacings.

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A 2.4 GHz Transceiver for Wireless Communication
Project Assistant :   Eric Haakenson
Project Director  :   Dr. Prasad Shastry
May 1994
This project was supported by a research grant from Northrop Grumman Corp.

ABSTRACT
   This report covers the microwave circuit development processes from specification to fabrication and testing for a system for wireless video communication. It also covers the performance of the Northrop NCTR2400 MMIC prototyper Transceiver for Wireless Communications. The circuit designs, computer aided simulations as well as ther measured performance characteristics are presented.

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A 2-13 GHz Monolithic Power Amplifier
Project Assistant :   Ashok Kajjam
Project Director  :   Dr. Prasad Shastry
June 1994
This project was supported by a research grant from Northrop Grumman Corp.

ABSTRACT
    Design and layout of a two-stage GaAs monolithic power amplifier covering the 2-13GHz band are presented in this report. This report also discusses the broadband design of the power amplifier. Computer simulated and measured results are presented. The 1.15mm X 1.15mm two-stage reactively matched single ended amplifier chip has 12dB gain in the frequency band 2-9GHz. Maximum calculated linear power of the amplifier is 108mW.

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2-13 GHz GaAs MESFET Distributed Amplifier
Project Assistant :   Srinivas Reddy Ponnala
Project Director  :   Dr. Prasad Shastry
June 1994
This project was supported by a research grant from Northrop Grumman Corp.

ABSTRACT
    A 2-13GHz cascaded-cell distributed amplifier has been designed, simulated, and implemented for microwave applications. The amplifier was designed using Triquint QED process MESFETS. Initially small signal and large signal modelling was performed using measured S-parameters and DC-IV curve data of a 300Micrometer MESFET. As per the design requirements the MESFET models were scaled accordingly. The operating principle of the amplifier is similar to a conventional distributed amplifier. The cascaded-cell distributed amplifier is different in topology and gives higher gain bandwidth product than the conventional distributed amplifier. Design of the amplifier using input and output capacitances, and new procedures to design interstage matching networks over the frequency range are presented. Final layout simulations and measurements are also presented.

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A Push-Pull Distributed Amplifier
Project Assistant :   G.Brubaker
Project Director  :   Dr. Prasad Shastry
June 1992
This project was supported by a research grant from Northrop Grumman Corp.

ABSTRACT
    The Push-Pull Distributed Microwave Amplifier is composed of several amplifier stages. First, a description of the fundamental concepts of the amplifier will be presented in order to clarify its operation and design considerations. Second, the amplifier will be subdivided into 'cells' which will facilitate design and analysis considerations. Finally, with the amplifier cell sections connected together, the operation of the complete amplifier will be discussed and the results of the computer-aided simulations of the 2-6 GHz amplifier will be presented.

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A 2-40 GHz HEMT Distributed Amplifier
Project Assistants :   Srinivas Reddy Ponnala
                                   Ashok Kajjam
Project Director    :   Dr. Prasad Shastry
May 1992
This project was supported by a research grant from Northrop Grumman Corp.

ABSTRACT
   Coming soon...

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A 2-26 GHz Distributed Power Amplifier
Project Assistant :   Srinivas Reddy Ponnala
Project Director  :   Dr. Prasad Shastry
August 1992
This project was supported by a research grant from Northrop Grumman Corp.

ABSTRACT
   Coming soon...

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Wireless LANs - A Technology Status Report
Project Assistants :   Srinivas Reddy Ponnala
                                   Ashok Kajjam
                                   Surendra Makam
Project Director    :   Dr. Prasad Shastry
December 1992
This project was supported by a research grant from Northrop Grumman Corp.

ABSTRACT
   Local area networks (LANs), are becoming increasingly important as a means of connecting a wide variety of devices such as computers, printers, intelligent terminals and so on. A network can be regarde as a series of separate nodes which are interconnected. Local area network is defined as a network with a limited geographical coverage. The concept of LANs began in order to share both hardware and software resources in an area, there by maximizing cost-effectiveness.
   The networks are classified into two categories based on the physical interconnection of the nodes. If the nodes are connected with a 'cable' or 'wire' it is known as wired Local Area Network (Wire LAN). If the nodes are connected without any 'wire' then it is known as wire-less Local Area Network (Wireless LAN).
   The most common local area network interconnections are through a physical media, such as twisted pair, coaxial cable and optical fibers. Both analog and digital signals can be transmitted trhough these media. In optical fibers, information is transmitted in the form of light. A 1 km typical cable can handle data rates of 10 Mbps and a typical 1 km optical fiber can handle a data rates of 1000 Mbps. Recent technological advances have enabled wireless LANs to use infrared, laser, microwave and RF signals. Digital signals are transmitted and received through air medium. Typical data rates of 1 to 10 Mbps are possible.
   The wired interconnections are difficult to install, maintain and change. These disadvantages are overcome in Wireless LANs. Both wire and wireless systems can be designed using various types of network topologies and architecture. The Wireless LANs are useful, particularly for: new installations where no usable cabling exists, difficult to cable environments, temporary installations, rapid deployment, and mobility. In this report, the network topologies and architecture, the types of wireless LANs and their merits & demerits, selected commercially available product information and their comparisons are presented.

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