End of semester

As the end of the semester is here, the current state of the hardware of the project is as follows. The layout should be done, barring any unforseen problems. It remains realatively unchanged, mostly I just checked to make sure the sizes of parts were correct.
The VHDL / Triggering part is nearly done. The current code that I have should work, and there are no "errors" but for some reason it will not compile on the machines at lab. It runs out of virtual memory. I'm going to install Xilinx at home and see if I can get it to compile on a machine with 4x as much memory. Other than that, a few communication links from the FPGA to the PC need to be included, but they are relatively simple to impliment.