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October 2005
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Home » Archives » October 2005

Thursday, October 20th

Sharpening C# and more


Most of my efforts have been focused on gathering applications, documentation, previous work and learning C#. The project website was moved from my personal webspace into the project webspace after Dr. Malinowski gave me permissions to upload to the project directory.

Jeff and I talked to Nick Schmidt (Asst. Lab Director) to install FrontPanel software from the Opal Kelly website and Xilinx ISE WebPACK 7.1i, so Jeff could start communicating with the XEM3001 board.I have been learning C# from MSDN C# Language Specification. I realized that there are a lot of things that are done differently in C# as compared to C++ and Java, both of which I am pretty familiar with. The way that variables and objects are declared is diffrerent, but dynamic so that is beneficial. I expect to run into some syntax errors to begin with.

I covered some basics on using the compiler and ran a few tutorials before starting on the Language Specifications. So far I have covered types and typecasting and the general mode of data handling. I will have to finish going through the following topics before I can dive into reviewing/writing code
for the project:

* Classes - a more indepth look
* Interface
* Namespaces
* Member functions
* Member access
* Application Handling
* Automatic Memory Management


shom on 10.20.05 @ 06:15 PM CST [permalink]

Thursday, October 13th

Electronic Lab Notebook


This project will use an Electronic Laboratory Notebook for record keeping instead of a traditional paper notebook. Lot of research was done to find a suitable and reliable solution.

After setting up the lab notebook, I researched the XEM3001 FPGA board and familiarized myself with the documentation available. After I am more familiar with the Opal Kelly documentation, I will look into last year's code and then try some C# tutorials and get my feet wet. Software needs to be installed on the lab computers. Hopefully that will happen soon so Jeff can start testing with last year's software.More on the Electronic Lab Notebook: The key factor was to find a solution where in the information entered could not be digitally altered, which requires a strong encryption. The information also needed to be globally accessible, so it has to be stored in an open format and finally the information needs to be timestamped. The first two concerns were remedied by using OpenOffice.org 2.0 from Sun Microsystems Inc. as the data entry and storage format. Using a portable document format [PDF] add-on the notebook installments will be published in PDF format with 128bit encryption.

Several more hours of researching online provided the solution to the time stamp problem. The PDF document will then be timestamped using an open source time-stamping software from http://www.timestamp.cyber.ee/ . The time-stamping service using a security certificate on a remote server to digitally sign the document and encloses it in a timestamped format (*.timestamp). The validator program, that is part of the package, opens the timestamped document and shows the time that was stamped by the trusted Time Stamp Authority [TSA] and allows for the document to be opened or saved in the original format.

Further the lab notebook will be maintained as individual documents for each day that the progress is recorded for. At the end of each session that the notebook is worked on, the session's document will be converted to encrypted PDF format and then timestamped.


shom on 10.13.05 @ 04:49 PM CST [permalink]

Thursday, October 13th

Pre-work on project


Ok, this entry will serve a dual purpose; refresh readers on the hardware portion of the project, and then cover the work done thus far by me (Jeff) while Shom was working on senior lab.

Hardware is responsible for bringing data in, triggering, and sending it to the PC. Those 3 things comprise the scope of the hardware portion of the project.

The work done thus far, has focused on learning how to use the OrCAD design program so I can make a board layout later on in the year.Ok, for those of you who wanted more of a detailed answer on what the hardware is doing...

The hardware will be bringing in data from 16 lines. The previous year's design will work well as a basic approach, but will need improvement in order to reduce cross-talk between lines, and to have the full 16 line system. At this point, I'm not sure if I'll be using a ribbon cable or not. We'll see later on.

As far as triggering, last year I looked into it, and decided that it was too late in the year to tackle the problem, and a simple solution could be implemented in software so we could get a more or less working prototype. However, this year I will be doing the triggering on the FPGA so that the perposterous amount of data thats being collected doesn't have to be sent across USB. That creates addition design issues that will need to be addressed. Last year's FPGA program will need to be more or less copmletely redesigned to take into account the new task while keeping the speed.

As a result of all that, the way data is sent to the PC will also have to change. Previously a rather handy function written by the Opal Kelly designers was used. This function simply took up to 2047 bytes of data (which at bits per line, and 16 lines, is not very many points), using a FIFO structure, and sent it to the PC when requested. Now, I will have to design my own larger FIFO memory array, and use one of the other more complicated fucntions to send data to the PC.

As far as what I've been working on thus far, I learned more or less how to design simple circuits in the OrCAD program suite. The suite was difficult to work with and it took me a few weeks just to figure out how to even get a one IC circuit in to the program. I still have a few things that I need to figure out, such as how to place non-IC parts in the system (like a ribbon cable mount and mounting holes). I also need to figure out how I will mount the XEM to my designed board and design a power system if its going to be manufactured.

The other work I did, was just planning out what I'll need to be doing, like the stuff I discussed at the beginning of this entry.


jeff on 10.13.05 @ 11:12 AM CST [permalink]

Tuesday, October 4th

USB Logic Analyzer


The goal of this project is to continue design for a USB logic analyzer to be used in the junior labartory. The design uses an Opal Kelly XEM3001 FPGA board which communicates over USB 2.0 to a GUI written in C#.The project was initially started by Jason Nielsen and Jeff Earleson in 2005. Previous work on this project has been recorded on their project website. Jeff Earleson will be working on the hardware part of the project again as an external consultant/designer. Shom and Jeff will both post updates on the their respective part of the project. Shom will be responsible for all deliverables pertaining to the Capstone Senior Project.


shom on 10.04.05 @ 03:50 PM CST [permalink]

Tuesday, October 4th

Development Blog

This blog will record the development/progress/issues/any relevant information about the USB Logic Analyzer Project. More to come later!


shom on 10.04.05 @ 01:01 PM CST [permalink]


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