[Previous entry: "Live Demo @ the Bradley Student Expo"]
04.26.2006: "Project Completion and Final Presentation"
The USB Logic Analyzer is a fully functional standalone software application now. It is interfaced with the XEM3001 FPGA board and it reads simulated data (8-bit binary counter) from the FPGA over USB correctly. I was able to figure out how to communicate with the FPGA board and read the buffer and then use part of Jason's C++ program from last year to parse the data correctly. Since there is no external PC board (hardware part of the project was terminated when Jeff left the project) to sample signals the FPGA puts an 8-bit binary count value in the buffer, which is a great way to demonstrate functionality.
On the software side there have been tons of additions. I added in a data bus, I was able to read the logic lines and combine them into a hex value that is displayed on the plot surface. The user has the ability to select the lines added to the bus independent of the lines being plotted. The user can also save the plot in image format (png, jpeg, bmp, and gif) or in numeric format (csv). The saved CSV data file can be loaded back into the application in the future and all the software features can be used for analysis. The screen shot of the application visually explains a lot of these features.
The project will be presented to faculty and students at the Senior Capstone Presentations on April 27th (tomorrow) at 8:30am. The presentation will be made available as part of the deliverables at later date. The final demonstration of the project will take place in Senior Lab on Friday, April 28th between 12 and 1 pm.
The final post to this website will be made once the final report has been approved for submission, at which point the project will be completed and all deliverables will be available here.