From: Jennifer Dilliner & Melissa DePriest

Date: October 30, 2001

Subject: Senior Project Functional Description

Title: Hamming Code Error Detector/Decoder

Advisor: Dr. Vinod Prasad
 
 

The (7,4) Hamming Code Error Detector/Decoder is a reliability-based circuit. This circuit consists of several inputs and outputs. It will accept a 7-bit signal from an outside source. This forms the "b vector." This vector consists of four bits of information and three bits of parity and will be stored in a 7-bit register. In addition to this, a three by seven matrix (the "H matrix") will be formed using three supplementary 7-bit registers. Three 7-bit error-checking vectors will be input to these registers and held by 21 tri-state devices (three sets of seven).  Diagram 1 and Diagram 2 will help clarify this description.

Each of the tri-state devices will be controlled by circuitry which will allow the data to be released (seven bits at a time) as needed in the error detection process. The "H matrix" and the "b vector" will be multiplied to form the 3-bit "S vector." This vector will indicate if the "b vector" input to the system is corrupt or correct.

If the "b vector" is corrupt, a signal will be transmitted back to the source to indicate the need for a retransmission of the data. However, if the "S vector" indicates that the "b vector" is not corrupt, the "b vector" will be sent through decoding circuitry and the 4-bit decoded data will appear on the output.

Initially, the circuit will be designed at the gate level utilizing LogicWorks. Then the circuit will be implemented into VLSI using L-edit. If time permits, the gate level circuit will be translated into VHDL code for implementation onto one chip.
 
 

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