From: Jennifer Dilliner & Melissa DePriest
Date: October 30, 2001
Subject: Complete System Level Block Diagram
Title: Hamming Code Error Detector/Decoder
Advisor: Dr. Vinod Prasad
Overall system
The overall system receives, from a source, a 7-bit vector input that
consists of four bits of information and three bits of parity. The system
also contains three 7-bit error-checking vectors. The system will output
a signal indicating whether or not the signal input was correct as well
as a 4-bit information vector decoded from the b vector if the input was
correct. The various subsystems are described below. Diagram
1 describes the subsystems in tabular format. Diagram
2, a detailed block diagram, will help clarify the following
descriptions.
B vector
The b vector is the 7-bit vector input from the source, which is stored
in a 7-bit register. If the signal is correct, the vector will be decoded
and output from the system as a 4-bit vector. If the signal is incorrect,
the vector will be retransmitted by the source and restored in the 7-bit
register.
H matrix
The H matrix is a three by seven matrix, which takes its input from
three 7-bit error-checking vectors. The vectors are stored in three 7-bit
registers. The data is then sent through three tri-state buffers that direct
which signal to be output into the matrix multiplier circuitry using a
controller.
Matrix Multiplier Circuit
The matrix multiplier circuit takes its input from the H matrix and
the b vector to form the new 3-bit vector, S. The circuitry will perform
the following function: H*b = S. The resulting S vector will be sent to
the error-checking subsystem for analysis.
Error Checking Circuit
This circuit detects if an error is present in the b vector transmitted
from the source. It receives the S vector and, through analysis of the
bits, outputs a signal to indicate if an error is or is not present.
Decoder Circuitry
The decoder subsystem receives the 7-bit b vector as input and decodes
the signal by removing the three parity bits and outputting a 4-bit information
vector.
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Diagram 1: Subsystems with I/O Descriptions
Diagram 2: Complete Block Diagram