PATENT SEARCH:

Internet Search- Applicable Patents.

Searched in http:// www.delphion.com

KEYWORD: "DATA MOVER" (I obtained 20 hits)

• Patent #US4296465: Data mover
• Patent # US5944797: Data mover hardware controlled processing in a commanding system and in a commanded system for controlling frame communications on a link

Inventor: Lemak Nicholas S., Phoenix, AZ

Abstract:

A data mover for moving blocks of data stored in a first location of the working store of a data processing system to a second location in the working store. The data mover is provided with the necessary registers, switches, counters and control circuits to issue read and write commands to the working store, to receive and store in registers data read out of the working store as the result of its having issued a read command, and to write data read out of working store and stored in its registers in response to a read command issued by the data mover into another location in the working store. These steps are repeated until a block, measured in thousands, of data words has been moved from the first to the second location. The address preparation circuits of the high speed multiplexer of the data processing system through which the data mover communicates with the working store of the system is used to provide a substitute memory command for one of the two types of memory commands issued by the data mover. Between the time the data mover issues a read command, and receives back from memory the data read out of memory in response to such a command, the data mover can issue a write command and transfer to the high speed multiplexer data received in response to the previous read command.
 
 
 
 

What is claimed is:

1. A data mover comprising:

• a data in bus;
• a data out bus;
• a control bus;
• data register means connected to the data in bus for storing at
• least one data word;
• control register means connected to the data in bus for storing at
• least one control word;
• means connected to the data out bus for issuing memory read
• commands and memory write commands; and
• control means connected to the control bus, to the data register
• means, and to the means for issuing memory commands for
• causing the means for issuing memory commands to issue a write
• command after issuing a read command on the data out bus only if
• a data word is stored in said data register means in response to a
• previously issued read command and to issue the data words
• stored in the data register means on the data out bus immediately
• following the issuing of write command.

Patent # US5944797: Data mover hardware controlled processing in a

commanding system and in a commanded system for controlling

frame communications on a link.
 
 
 
 

Abstract:

The present invention significantly reduces or eliminates the involvement of central processors in the message block handling of received communication-link responses within a Central Processing Complex (CPC). When a commanding system sends a command, it must receive a response frame from the commanded system indicating if

the command was correctly received or not. A significant amount of time is required for the commanding system processor to move the received response frame from a

receiving link buffer to an area in the CPC memory. The preferred embodiment avoids the need for having a commanding system processor either wait for or be

interrupted to handle the response frame. The preferred embodiment provides advanced preparation of a data mover in a manner to enable the data mover in the

computer system to handle the reception of each response frame without involving the commanding system processor. The commanding system is signaled by the

data mover on the completion of the response handling to make the completion of each command known to the program which issued the command.

What is claimed is:

Having thus described our invention, what we claim as new and desire to secure by Letters Patent is:

1. A method of handling link response frames responding to command frames sent on a link by a commanding computer system to a commanded computer system, comprising the steps of: preparing by a processor in the commanding computer system blocked areas in a memory of the commanding computer system for use by a data mover implemented in hardware of the commanding computer system, the blocked areas including: a message command block (MCB) and a message response block (MRB), a link control block (LCB), and assigning the areas to a subchannel for use by a send message instruction to be issued by the commanding computer system, issuing of a send message (SM) instruction by the processor, including a SM command to the data mover, and the data mover sending to the commanded computer system a command frame on the link containing command information prepared in the area assigned to the subchannel, receiving the command frame by the commanded computer system, preparing by the commanded computer system a response frame indicating status of response to a command received in the command frame, and sending a response frame on the link to the commanded computer system, receiving the response frame by the data mover at the commanding computer system, and processing the response frame for error conditions and moving information from the response frame to the commanding system memory for access by the program issuing the command resulting in the response frame, and signaling by the data mover to an available processor in the commanding computer system of a completion of execution of the SM instruction, for which the data mover accesses and stores information in a link control block (LCB) in a memory of the

commanding computer system using an LCB address in a register of the data mover.
 
 
 
 

STANDARDS SEARCH

Internet Search

http://www.nssn.org/

KEYWORD "CMOS" (123 hits)

• Document Number: JEP116. Title: CMOS Semicustom Design Guidelines

• Document Number: JESD80. Title: Standard for Description of 2.5 V CMOS Logic Devices.

KEYWORD "CMOS IN VLSI" (0 hits)

• NO APPLICABLE STANDARD

• NO APPLICABLE STANDARDS.

Uyemura, John P. Physical Design of CMOS Integrated Circuits Using L-Edit.
Boston: PWS Publishing Company. 1995.

Mukherjee, Amar. Introduction to NMOS & CMOS VLSI Systems Design

Dr. Vinod B. Prasad. Teacher of the class EE563 in  Bradley University.