Figure 1a:
Potentiometer Output to A/D Input Block Diagram
Figure 1b:
D/A Output to Power Amplifier Input Block Diagram
Project Title:
Microcontroller Implementation of a Small Robot Arm Controller
Week of: January 25th, 2000
Engineers:
Megan Bern and Ritesh Patel
Advisor’s Signature: _________________
Grade: _______
=================================================================
Objective:
For the week of January 25th, 2000, our objective was to build and test the interface hardware, which was previously designed and simulated on PSPICE, and write code for a digital filter.
Progress:
Hardware:
The initial problem was that the potentiometer and the power amplifier that drives the motor operate over a range of +5V to -5V. The analog-to-digital (A/D) and digital-to-analog (D/A) converters only operate over a range of 0V to +5V. The block diagrams shown in Figure 1a and Figure 1b were used as linear models for designing the interface hardware.
Figure 1a:
Potentiometer Output to A/D Input Block Diagram
Figure 1b:
D/A Output to Power Amplifier Input Block Diagram
The schematics shown in Figure 2a and Figure2b are the designs used to implement the linear conversions needed to interface the potentiometer and power amplifier with the A/D and D/A converters.
Figure 2a:
Potentiometer to A/D Converter Design Interface
Figure 2b:
D/A Converter to Power Amplifier Design Interface
The schematics shown in Figure 2a and Figure2b was built using the LMC6482AIN Dual Rail-To-Rail Input and Output Operational Amplifier. The equipment needed to test the hardware is listed in Table 1.
1. FLUKE 45 Dual Display Multimeter EQ-2203.
2. Tektronix TDS 340A Digital Real-Time Oscilloscope EQ-2151.
3. Hewlett Packard 6215A Power Supply EQ-577.
4. Hewlett Packard E3630A DC Power Supply EQ-2008.
The circuit shown in Figure 2a was the
first to be tested. A range of possible inputs from a potentiometer
were input into the circuit and the outputs were displayed and measured
on the oscilloscope. These measurements are shown in Figure 3.
Figure 3: Inputs vs. Experimental Outputs for P to A/D
Table 2a lists the inputs to the circuit as well as the expected and experimental values.
Table 2a:
Inputs vs. Outputs for P to A/D
Potentiometer Calculated
Experimental
5.00V
5.00V
4.80V
2.50V
3.75V
3.70V
0.00V
2.50V
2.60V
-2.50V
1.25V
1.30V
-5.00V
0.00V
0.00V
The experimental values are off by a maximum of 200mV. The feature of interest for the LMC6482AIN is that the Rail-To-Rail Output Swing ranges within 20mV of the supply rail with a 100 k? load. The design contains a 1k? load. This is why the experimental output was 200mV out of range.
The circuit shown in Figure 2b was also tested. A range of possible inputs from a D/A converter were input into the circuit and the outputs were displayed and measured on the oscilloscope. Table 2b lists the inputs to the circuit as well as the expected and experimental values.
Table 2b:
Inputs vs. Outputs for D/A to AMP
Potentiometer
Calculated Experimental
5.00V
5.00V
4.80V
3.75V
2.50V
2.50V
2.50V
0.00V
0.00V
1.25V
-2.50V
-2.50V
0.00V
-5.00V
-4.80V
These values are also off by 200mV. To fix the problem we increased the load to 100k?. The circuits were both tested again and measured this time with the multimeter. The recorded values for both circuits are shown in Table 3a and Table 3b.
Table 3a:
Inputs vs. Outputs for P to A/D with new load
Potentiometer
Calculated Experimental
5.00V
5.00V
4.998V
2.50V
3.75V
3.7774V
0.00V
2.50V
2.511V
-2.50V
1.25V
1.249V
-5.00V
0.00V
-0.013V
Table 3b:
Inputs vs. Outputs for D/A to AMP with new load
Potentiometer
Calculated Experimental
5.00V
5.00V
4.898V
3.75V
2.50V
2.439V
2.50V
0.00V
-0.018V
1.25V
-2.50V
-2.477V
0.00V
-5.00V
-4.938V
These values were better
than the values with only a 1k? load. The values in Table 3b are
off by a maximum of 102mV. This is more than 60mV(20mV per op-amp)
that the specifications will allow. Next week this problem will be
looked at a little closer. It is possible that the component values
are not exact and that could make the output out of range.
The final schematics with the new 100k? loads are shown in Figure
4a and 4b.
Figure 4a:
Final schematic for P-to-A/D conversion
Figure 4b:
Final schematic for D/A-to-AMP conversion
Software:
The following analog filter shown in Figure 5 is a low-pass filter. This filter will be implemented in assembly language.
Figure 5:
Digital Filter
This digital filter is represented by the transfer function shown by (1). The single pole is located at 200 Hz. A 20 Hz single pole will be used later.
(1)This equation is converted to z-plane form using the Tustin Method (bilinear transformation). The variable s is replaced by (2) where T=fixed sampling period=0.0005s. The transfer function in z-plane is shown in (3).
The steady state value
of the filter is 1.0, so (7) should add up to 1.0. Equation 7 is
rounded up to (8) to make it easier to write in code. This equation will
be implemented in assembly language.
To implement this
equation on the EMAC board, a sine wave was generated to check if the A/D
and D/A converters are working properly. A sine wave was input into
the A/D converter. The D/A should output the same sine wave if the
EMAC board is working properly. The code that was used to accomplish
this task is attached to this report.
After running the code, the output shown in Figure 6 was displayed
on the oscilloscope. The input was a 200 Hz sine wave. The
output was also a 200 Hz. This means that the EMAC board was working
properly.
Figure 6: A/D input vs. D/A output
Next week, the code
for the digital filter will be written and tested if time permits.
;Ritesh Patel & Megan Bern
;Program1
;01/25/00
;generates 10Hz square wave
;A/D and D/A conversion
;include(mod515)
$INCLUDE(mod515)
STARD EQU 8000H ;start address for program
ORG stard
JMP SETUP
;Interrupt Jump Table
org stard+2BH
;TF2 + EXF2 interrupt
AJMP TMR2SRV
; Jump to timer 1 interrupt
;-----------------------------------------------------------------
TMR2SRV:
;timer 2 service every 50 ms
CPL p4.1
;generate pulse
CLR TF2
;clear interrupt flag
RETI
;***********************************************
;
;
Intialization Code
;
;***********************************************
SETUP:
MOV IEN0,#0 ;Disable
ALL INTS
MOV SP,#70H ;Initialize
STACK
SETB P5.5
;Do a reset
CLR P5.5
;bring it low
SETB P5.0
;make A16 of 128K Ram, high
SETB P5.2
;disable EEPROM
CLR P5.1
;new port 5.1 for D/A
;END 80535 Stuff
MOV R0,#7FH ;CLEAR 128 BYTES OF RAM
clr_ram: MOV @R0,#0
DJNZ R0,clr_ram
SETB T2CON.0 ; timer 2: 16 bit operation
SETB T2CON.4 ; and
auto-reload mode
MOV TH2,#4CH ; load timer
2 registers
MOV TL2,#01H
MOV CRCH,#4CH ; load capture
registers
MOV CRCL,#01H ; timer 2
SETB ET2
; enable timer 2 ovf int
SETB EAL
; enable all interrupts
main:
MOV A,#2 ; load ACC for channel 2
CALL adcin ; call converter subroutine
; value in ACC
CALL da_out ; write to D/A converter, Chn 0
JMP main ; loop forever
; ADCIN subroutine
; Return ACC with the 8 bit A/D conversion from the channel
selected by ACC
;
ADCIN:
ANL A,#00000111B
; ONLY 8 CHANNELS
ANL ADCON,#11000000B
; MODE FOR A/D CONVERSION: SINGLE
ORL ADCON,A
; "OR" IN THE CHANNEL
MOV DAPR,#0
; START CONV W/NO REF VOLTAGE
JB BSY,$
; LOOP TILL CONVERTED
MOV acc,ADDAT
; ACC = CONVERSION
RET
; da_out subrountine
; write value in ACC to D/A channel specified below
DA_0 Equ 10H
DA_1 Equ 11H
DA_2 Equ 12H
DA_3 Equ 13H
da_out: MOV P2,#DA_0
; point to D/A channel 0
MOVX @R1,A
; write data
RET
END