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A Shift Decoder Digital Hardware System for Monitoring Transmission Operations
by
Tony Grebner & Dan Jakubowski
Advisor: Dr. V. Prasad
A Shift Decoder design containing digital hardware using TTL logic has
been designed and tested for successful operation. The memory addresses
are produced internally by Up/Down counters or externally by transmission
pressure cells consisting of a bridge circuit with either mode displayed
on two. 7-Segment LEDs. The programmed digital input is provided by two,
4-Bit BCD Thumbwheel switches and stored in the memory. The data corresponding
to the address location representing a particular gear is converted to
an analog voltage in a selected output range produced by operational amplifiers.
Consequently, the circuit is intended to monitor the transmission operation
of industrial vehicles by "decoding" digital bits to a voltage for each
gear change.
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