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Fault Detection and Analysis for Combinational Logic Circuits
by
Rod DeMay & Glenn Losinski
Advisor: Dr. V. Prasad

Fault detection and analysis is a means of saving valuable time troubleshooting circuits. Our project provides a way of even further reducing the time to troubleshoot a circuit using a personal computer, digital I/0 board, and Turbo C. We will present the various uses our program offers to the users. General fault analysis will be described with respect to combinational logic circuits. A comparison of a graphical approach to a computational approach will be discussed. Brief overview of critical algorithms used will given.
 

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